(1) Field of the Invention
The present invention relates to the fabrication of dynamic random access memory, (DRAM), devices, and more specifically to the process and apparatus used to produce DRAM structures with increased capacitance.
(2) Description of Prior Art
A critical parameter of a DRAM device is the ability of the storage node, of the DRAM device, to supply the desired capacitance needed for circuit performance. The basic DRAM memory cell is usually comprised of a transfer gate transistor and a connected capacitor. Charges are stored in the capacitor section of the DRAM, and are accessed via the transfer gate transistor. The ability to densely pack storage cells, while maintaining sufficient stored charge, is a function of the type and structure of the capacitor of the DRAM device. One method used by DRAM manufacturers, for capacitors, is the stacked capacitor cell, (STC), structure. This structure consists of two conductive layers, for example polysilicon, with a thin dielectric, or thin composite dielectric layer, between the polysilicon layers, with the capacitor structure overlying, and contacting, specific regions of an underlying transfer gate transistor.
However as DRAM densities increase, resulting in smaller device dimensions, the ability to maintain adequate capacitance using the STC structure becomes difficult. The decreasing dimensions of the transfer gate transistor limits the dimensions of the overlying capacitor plates, thus severely limiting the ability to maintain the capacitance needed to operate the DRAM device. Alternatives for maintaining device signal, or capacitance, include decreasing the thickness of the dielectric layer, between the conductive polysilicon layers. However it is difficult to decrease the thickness of the dielectric layer much below 100 Angstroms, in silicon dioxide equivalent, without risking yield or reliability concerns. Therefore the industry has attempted to address the capacitance issue by increasing the area of the conductive plates, while still maintaining, or even decreasing the dimensions of the underlying transfer gate transistor. This has been accomplished by producing a polysilicon layer, used as a lower conductive plate, with the polysilicon exhibiting a roughened, or a hemispherical grained, (HSG), surface. The HSG polysilicon surface, with concave and convex features, results in a significant increase in surface area, when compared to counterparts with flat polysilicon surfaces, and thus resulting in increased capacitance of the STC structure, without increasing the dimensions of the DRAM cell.
The ability to create HSG polysilicon layers, with the maximum level of roughness is dependent on deposition parameters and apparatus. A pending application, 08/450,299, describes a narrow temperature range for obtaining the maximum polysilicon HSG roughness. Other descriptions for producing HSG polysilicon layers have also been supplied, previously by Hayashide, et al, in U.S. Pat. No. 5,290,729, as well as Fazen, et al, in U.S. Pat. No. 5,278,091. However these descriptions do not teach the processes needed to obtain the uniformity of polysilicon HSG roughness, from wafer to wafer, in a specific deposition tool.
This invention will describe a process and a deposition tool, in which the desired narrow temperature range, and the desired consistent reactant concentration, needed to maximize the HSG roughness across the length of the deposition tool, is achieved.